1. Field of the invention
The present invention relates to a semiconductor memory circuit, and more specifically to a bit line load circuit for use in a semiconductor static RAM (random access memory).
2. Description of related art
Conventional static RAMs have been composed of a number of complementary bit line pairs, each bit line pair being connected to a bit line load circuit, and also connected through a column selection circuit to a pair of complementary data bus lines which are connected to an input/output data control circuit. To each bit line pair, a number of static RAM memory cells are connected, and the memory cells connected to the same bit line pair are connected to different word lines, respectively.
The bit line load circuit includes a pair of bit line precharge transistors connected between a voltage supply potential and a corresponding pair of bit lines, respectively, and an equalizing transistor connected between the pair of bit lines. A control electrode of the bit line precharge transistors and the equalizing transistor are connected in common to receive the same precharge signal. When the precharge signal is activated, all of the bit line precharge transistors and the equalizing transistor are turned on, so that the pair of bit lines are precharged to the voltage supply potential through the bit line precharge transistors, and the potential of the pair of bit lines are equalized by action of the turned-on equalizing transistor.
Some type of bit line load circuit known to the inventor further includes a pair of bit line level compensating transistors each connected in parallel to a corresponding one of the pair of bit line precharge transistors. These bit line level compensating transistors are formed of a P-channel transistor having its gate connected to the ground, so that the bit line level compensating transistors are ceaselessly maintained in a conductive condition.
In a reading operation, after the pair of bit lines have been precharged to the voltage supply potential during an active period of the precharge signal, the selected word line is activated, so that either one of the pair of bit lines is discharged in accordance with information stored in the selected memory cell. Namely, the potential of the one of the pair of bit lines gradually drops from the voltage supply potential. However, since the bit line level compensating transistors are ceaselessly maintained in the conductive condition, the potential of the one bit line does not drop to the ground level, but the potential drop of the one bit line stops at a predetermined potential. This is to prevent the data held in a memory cell connected to the word line selected in a next reading cycle, from being broken by a potential elevation of the word line selected in that next cycle. In addition, it is effective in speeding up the equalizing operation in a next precharge cycle so that the reading operation can be carried out at a high speed.
Accordingly, after the reading operation has been completed, when the precharge signal is activated again, the bit line precharge transistors and the equalizing transistor are turned on, so that the pair of bit lines are precharged and equalized and are quickly elevated to the voltage supply potential.
In the above mentioned bit line load circuit for the semiconductor static RAM, however, since the bit level compensating transistors are constituted of the P-channel transistor ceaselessly maintained in the conductive condition, the drop speed of the bit line potential in the reading operation is slow, with the result that the total reading speed is low.